PCT Publication WO2007/004253 A1 discloses a non-volatile semiconductor memory device of a reduced readout time of control information during an initial setting period when powered on or reset. According to PCT Publication WO2007/004253 A1, a plurality of non-volatile memory cells, hereinafter called active cells, connected to a single bit line or a single word line stores the same control information of one bit. When reading out the control information, as the information is simultaneously read out from a plurality of active cells for each bit, a data current of several times more than normal is obtained. Consequently, as a driving capability of a readout route is reinforced, not requiring a voltage amplification while reading out the control information, and allowing a readout time to be reduced during an initial setting period when powered on or reset, the device promptly moves on to a normal access operation.
Japanese Patent Application Publication No. JP-A-H11-307746 discloses, in order to prevent a voltage rise of a source line, a non-volatile semiconductor memory device provided with a dummy source line in a cell array. Japanese Patent Application Publication No. JP-A-2001-110920 discloses, in order to adjust a bulk voltage, a non-volatile semiconductor memory device provided with a bulk bias contact structure in a cell array.